• Reconfigurable Architectures (Wednesday 10:30AM-Noon)
    Room A108/110/112
    Chair: Steve Reinhardt, Silicon Graphics Inc.

    • Title: Delivering Acceleration: The Potential for Increased HPC Application Performance Using Reconfigurable Logic
    • Authors:
      David Caliga (SRC Computers, Inc)
      David Peter Barker (SUPERsmith)
    • Abstract:
      SRC Computers, Inc. has integrated adaptive computing into its SRC-6 high-end server, incorporating reconfigurable processors as peers to the microprocessors. Performance improvements resulting from reconfigurable computing can provide orders of magnitude speedups for a wide variety of algorithms. Reconfigurable logic in Field Programmable Gate Arrays (FPGAs) has shown great advantage to date in special purpose applications and specialty hardware. SRC Computers is working to bring this technology into the general purpose HPC world via an advanced system interconnect and enhanced compiler technology.   

    • Title: Parallel Dedicated Hardware Devices for Heterogeneous Computations
    • Authors:
      Alessandro Marongiu (CASPUR, Roma)
      Paolo Palazzari (ENEA-HPCN, Roma)
      Vittorio Rosato (ENEA-HPCN, Roma)
    • Abstract:
      We describe a design methodology which allows a fast design and prototyping of dedicated hardware devices to be used in heterogeneous computations. The platforms used in heterogeneous computations consist of a general-purpose COTS architecture which hosts a dedicated hardware device; parts of the computation are mapped onto the former, parts onto the latter, in a way to improve the overall computation efficiency. We report the design and the prototyping of a FPGA-based hardware board to be used in the search of low-autocorrelation binary sequences. The circuit has been designed by using a recently developed Parallel Hardware Generator (PHG) package which produces a synthesizable VHDL code starting from the specific algorithm expressed as a System of Affine Recurrence Equations (SARE). The performance of the realized devices has been compared to those obtained on the same numerical application on several computational platforms.

    • Title: Cost Effectiveness of an Adaptable Computing Cluster
    • Authors:
      Keith D. Underwood (Clemson University)
      Ron R. Sass (Clemson University)
      Walter B. Ligon, III (Clemson University)
    • Abstract:
      With a focus on commodity PC systems, Beowulf clusters traditionally lack the cutting edge network architectures, memory subsystems, and processor technologies found in their more expensive supercomputer counterparts. What Beowulf clusters lack in technology, they more than make up for with their significant cost advantage over traditional supercomputers. This paper presents the cost implications of an architectural extension that adds reconfigurable computing to the network interface of Beowulf clusters. A quantitative idea of cost-effectiveness is formulated to evaluate computing technologies. Here, cost-effectiveness is considered in the context of two applications: the 2D Fast Fourier Transform (2D-FFT) and integer sorting.