• Architectures (Tuesday 10:30AM-Noon)
    Room A201/205
    Access Grid Enabled
    Chair: Burton Smith, Cray Inc.

    • Title: Scientific Computing on the Itanium (TM) processor
    • Authors:
      Bruce Greer (Intel Corporation)
      John Harrison (Intel Corporation)
      Greg Henry (Intel Corporation)
      Wei Li (Intel Corporation)
      Peter Tang (Intel Corporation)
    • Abstract:
      The 64-bit Intel{R} Itanium{TM} architecture is designed for high-performance scientific and enterprise computing, and the Itanium processor is its first silicon implementation. Features such as extensive arithmetic support, predication, speculation, and explicit parallelism can be used to provide a sound infrastructure for supercomputing. A large number of high-performance computer companies are offering Itanium{TM}-based systems, some capable of peak performance exceeding 50 GFLOPS. In this paper we give an overview of the most relevant architectural features and provide illustrations of how these features are used in both low-level and high-level support for scientific and engineering computing, including transcendental functions and linear algebra kernels.

    • Title: The Sun Fireplane System Interconnect
    • Authors:
      Alan E Charlesworth (Sun Microsystems, Inc.)
    • Abstract:
      System interconnect is a key determiner of the cost, performance, and reliability of large cache-coherent, shared-memory multiprocessors. Interconnect implementations have to accommodate ever greater numbers of ever faster processors. This paper describes the Sun Fireplane two-level cache-coherency protocol, and its use in the medium and large-sized UltraSPARC-III-based Sun Fire servers.

    • Title: Parallel Graphics and Interactivity with the Scaleable Graphics Engine
    • Authors:
      Kenneth A. Perrine (Pacific Northwest National Laboratory)
      Donald R. Jones (Pacific Northwest National Laboratory)
    • Abstract:
      A parallel rendering environment is being developed to utilize the IBM Scaleable Graphics Engine (SGE), a hardware frame buffer for parallel computers. Goals of this software development effort include finding efficient ways of producing and displaying graphics generated on IBM SP nodes and of assisting programmers in adapting or creating scientific simulation applications to use the SGE. Four software development phases discussed utilize the SGE: tunneling, SMP rendering, development of an OpenGL API implementation which utilizes the SGE in parallel environments, and additions to the SGE-enabled OpenGL implementation that uses threads. The performance observed in software tests show that programmers would be able to utilize the SGE to output interactive graphics in a parallel environment.