AWARDS CAP SC2001

HIGH-PERFORMANCE COMPUTING AND NETWORKING CONFERENCE

DENVER, CO — SC2001, the conference of high-performance networking and computing capped the most successful programs in its history by recognizing outstanding achievements and contributions in these fields.

The conference attracted nearly 200 exhibitors and over 5200 attendees, each of whom on average will spend between $3.5- and $7-million on planned purchases as a result of the week-long event.

The awards presented this afternoon honored a range of people and their accomplishments.

The primary award was the third annual IEEE Computer Society Seymour Cray Computer Engineering Award. This honor recognizes innovative contributions to high-performance computing systems that exemplify Seymour Cray’s creative spirit.

This year it was awarded to John L. Hennessy, President of Stanford University. Included is a $10,000 honorarium funded by an SGI endowment.

The Gorden Bell Prize is named after the Digital Equipment vice president. It is awarded annually at SC for the best peak computer performance, the best performance/price ratio and for a special category.

The Gordon Bell winner was the team of Toshiyuki Fukushige and Junichiro Makino, who achieved a simulation of black holes in a galactic center at a computer processing speed of 11.55 trillion floating operations per second.

The Gordon Bell Price/Performance prize went to Joon Hwang, Seung Kim and Chang Lee. Their study of impact locating on aircraft structure by low-cost cluster cost 24.6 cents/Mflops, or less than a U.S. quarter per 1-million floating operations per second.

The winner of the Gordon Bell Prize in the special category of supporting efficient execution in the heterogeneous distributed computing environments with Cactus and Globus. The winner was the team of Gabrielle Allen,Thomas Dramlitsch, Ian Foster, Nick Karonis, Matei Ripeanu, Edward Seidel and Brian Toonen.

The Best Student Paper was awarded to a computational grid application of tomography, a technique to reconstruct the three-dimensional structure of an object from a series of two-dimensional projections. The award went to a team of Shava Smallen, Henri Cazsanova and Francine Berman, and carries a $500 cash award.

Finally, the award for Best Research Poster went to Sumir Chandra, Johan Steensland and Manish Parashar.

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Reconfigurable Architectures

Chair: Steve Reinhardt, Silicon Graphics Inc.
  • Title: Delivering Acceleration: The Potential for Increased HPC Application Performance Using Reconfigurable Logic
  • Authors:
    David Caliga (SRC Computers, Inc)
    David Peter Barker (SUPERsmith)
  • Abstract:
    SRC Computers, Inc. has integrated adaptive computing into its SRC-6 high-end server, incorporating reconfigurable processors as peers to the microprocessors. Performance improvements resulting from reconfigurable computing can provide orders of magnitude speedups for a wide variety of algorithms. Reconfigurable logic in Field Programmable Gate Arrays (FPGAs) has shown great advantage to date in special purpose applications and specialty hardware. SRC Computers is working to bring this technology into the general purpose HPC world via an advanced system interconnect and enhanced compiler technology.
  • Title: Parallel Dedicated Hardware Devices for Heterogeneous Computations
  • Authors:
    Alessandro Marongiu (CASPUR, Roma)
    Paolo Palazzari (ENEA-HPCN, Roma)
    Vittorio Rosato (ENEA-HPCN, Roma)
  • Abstract:
    We describe a design methodology which allows a fast design and prototyping of dedicated hardware devices to be used in heterogeneous computations. The platforms used in heterogeneous computations consist of a general-purpose COTS architecture which hosts a dedicated hardware device; parts of the computation are mapped onto the former, parts onto the latter, in a way to improve the overall computation efficiency. We report the design and the prototyping of a FPGA-based hardware board to be used in the search of low-autocorrelation binary sequences. The circuit has been designed by using a recently developed Parallel Hardware Generator (PHG) package which produces a synthesizable VHDL code starting from the specific algorithm expressed as a System of Affine Recurrence Equations (SARE). The performance of the realized devices has been compared to those obtained on the same numerical application on several computational platforms.
  • Title: Cost Effectiveness of an Adaptable Computing Cluster
  • Authors:
    Keith D. Underwood (Clemson University)
    Ron R. Sass (Clemson University)
    Walter B. Ligon, III (Clemson University)
  • Abstract:
    With a focus on commodity PC systems, Beowulf clusters traditionally lack the cutting edge network architectures, memory subsystems, and processor technologies found in their more expensive supercomputer counterparts. What Beowulf clusters lack in technology, they more than make up for with their significant cost advantage over traditional supercomputers. This paper presents the cost implications of an architectural extension that adds reconfigurable computing to the network interface of Beowulf clusters. A quantitative idea of cost-effectiveness is formulated to evaluate computing technologies. Here, cost-effectiveness is considered in the context of two applications: the 2D Fast Fourier Transform (2D-FFT) and integer sorting.
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